Apparatus and a method for detecting the coincidence of two signal levels

ABSTRACT

An apparatus for detecting the coincidence of two input signals comprises a first unit for deciding elevation between two input signals, a second unit for connecting a low level signal selected from the input signals to one output path for the low level signal and connecting a high level signal selected from the input signals to another output path for the high level signal as determined by the decision output, a third unit for producing a tolerance level for deciding one input signal level is coincident with another input signal level, a fourth unit for adding the low level signal form the output path to the tolerance level, and a fifth unit for comparing the adding output with the high level signal from the output path, and deciding one input signal level is coincident with another input signal level if a level of the addition output is higher than a level of the high level signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and a method for decidingwhether one signal level is coincident with another signal level or not.

Detecting or deciding elevation or coincidence of two signal levels isrequired in various fields. For example, the diversity reception systemin a mobile communication system uses plural reception systems havinglittle correlation with each other and has to select one of thereception systems that has a higher signal level than the otherreception system. In such a case, it is necessary to detect elevation ofthe signal levels to change the reception systems and also coincidencethereof to start processes corresponding to detection of thecoincidence.

2. Description of the Related Art

It is possible to detect the coincidence of two signal levels by usingelectrical devices, e.g., an analog to digital (A/D) converter, adigital comparator, etc. Namely, the A/D converter converts an analoginput signal to a digital value of n bits. The digital comparatorcompares the digital values from two A/D converters and decides whetherone digital value is coincident with another digital value or not.

However, the conventional system as described above has to use two A/Dconverters for two analog inputs, thereby a circuit scale of the systembecomes large. Recently, the most significant priority for design of anapparatus is the miniaturization of the apparatus, therefore parts andcircuit scale of the apparatus must be small in size. However, thesystem as described above cannot satisfy the requirement of theminiaturization.

Further, the A/D converter has an adjusting circuit for adjusting itsfull-scale and a zero-point so that the circuit of the system is largerby adding the adjusting circuit. Furthermore, there is a problem that itis not easy to match the tolerance between the A/D converters so as notto decrease their detection accuracy by addition of the adjustingcircuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a detector fordeciding the coincidence of two signal levels, which has a small scalecircuit and no adjustment for the circuit, in order to solve theproblems described above.

According to the present invention an apparatus for detecting thecoincidence of two input signals comprises a first means for decidingthe elevation between two input signals, a second means for connecting alow level signal selected from the input signals to one output path forthe low level signal and connecting a high level signal selected fromthe input signals to another output path for the high level signal by adecision output from the first means, a third means for producing atolerance level for deciding one input signal level is coincident withanother input signal level, a fourth means for adding the low levelsignal from the output path of the second means to the tolerance levelfrom the third means, and a fifth means for comparing the added outputfrom the fourth means with the high level signal from the output path ofthe second means and deciding one input signal is coincident withanother input signal if the level of the added output is higher than thelevel of the high level signal.

Further, according to the present invention a method for detecting thecoincidence of two input signals comprises the steps of deciding theelevation difference between two input signals, adding a low levelsignal selected from the input signals by the decision to a tolerancelevel signal for deciding one input signal level is coincident withanother input signal level, comparing the result of the addition with ahigh level signal selected from the input signals by the decision, anddeciding one input signal level is coincident with another input signallevel if the level of the result of addition is higher than the level ofthe high level signal by the comparison.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from thedescription as set forth below with reference to the accompanyingdrawings.

FIG. 1 shows an example of a conventional detector that decides whetherone input signal level is coincident with another input signal level ornot.

FIG. 2 is a block diagram of a detector for deciding the coincidence oftwo input signal levels according to the present invention.

FIG. 3 is an explanatory view showing performance characteristics of thedetector in FIG. 2 according to the present invention.

FIG. 4 is a preferred embodiment of a circuit of the detector accordingto the present invention.

FIG. 5(A) and FIG. 5(B) are explanatory views that show the operation ofthe coincident decision circuit schematically.

FIG. 6 is a timing diagram of the output signals in FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the preferred embodiments according to the presentinvention, an example of the related art is provided with reference toaccompanying the drawings (FIG. 1).

FIG. 1 shows an example of a conventional detector for deciding oneinput signal level is coincident with another input signal level.

In FIG. 1, two A/D converters 10, 12 convert analog input signals V_(A),V_(B) to digital values of n bits and then provide each digital value toa digital comparator 18. The digital comparator 18 decides whether onedigital value is coincident with the other digital value or not. Theconventional detector provides simplicity and high resolution, and alsopermits variable tolerance in the decision of the coincidence of twoinput signal levels by providing a simple way of comparing the digitalvalues while excluding some of the lower bits of the digital values.

However, in the detector described above there are some problems in thatthe detector has to use two A/D converters 10, 12 so that the circuitscale of the detector becomes large, and each A/D converter 10, 12 hasto use an adjusting circuit 14, 16 respectively to adjust its full-scaleand a zero-point so that the circuit becomes even larger by adding theadjusting circuit 14, 16. Further, it is not easy to match the tolerancebetween the A/D converters 10, 12 by the adjusting circuit 14, 16 so asnot to decrease in their detection accuracy.

FIG. 2 shows a block diagram of a detector for detecting the coincidenceof two input signal levels according to the present invention.

In FIG. 2, a level comparator 21 compares one analog input signal V_(A)with another analog input signal V_(B), and decides the elevation of thetwo signal levels. A path switching circuit 22 has an interchangeablepath switched by an output signal S₂ from the level comparator 21,through which each signal V_(A), V_(B) is connected to either of anoutput path P_(L) Or P_(H). The output path P_(L) terminates the lowerlevel signal selected from the input signals V_(A), V_(B) and the outputpath P_(H) terminates the other higher level signal by the output signalS₂. A tolerance generator 23 produces a reference voltage V_(REF) thatcorresponds to a tolerance level for deciding one input signal (V_(A) orV_(B)) level is coincident with another input signal (V_(B) or V_(A))level.

A addition circuit 24 adds the reference voltage V_(REF) to the lowerlevel signal from the output path P_(L). A coincidence decision circuit25 compares the level of the addition output from the addition circuit24 with the level of the high level signal from the output path P_(H),and if the output level from the addition circuit 24 is higher than thelevel of the high level signal from the output pass P_(H), that is V_(B)>V_(A), V_(A) +V_(REF) >V_(B) Or V_(A) >V_(B), V_(B) +V_(REF) >V_(A),the coincidence decision circuit 25 decides one input signal level iscoincident with the other input signal level (V_(A) =V_(B)).

FIG. 3 is an explanatory view showing performance characteristics of thedetector in FIG. 2.

In FIG. 3, it is assumed that one input signal V_(A) is a constant andanother input signal V_(B) varies as shown by a broken solid line, anduntil a time t_(I) the signal level V_(A) is higher than the signallevel V_(B) (V_(A) >V_(B)) and after the time t₁ the signal level V_(A)is lower than the signal level V_(B) (V_(A) <V_(B)). Until the time t₁,the level comparator 21 decides V_(A) >V_(B) and outputs a high levelsignal S₂ (H), and conversely, after the time t₁ the level comparator 21decides V_(A) <V_(B) and outputs a low level signal S₂ (L). The pathswitching circuit 22 is provided with the signal S₂. If the signal S₂ ishigh (V_(A) >V_(B)), the path switching circuit 22 connects the lowlevel signal V_(B) to the output path P_(L) and connects the high levelsignal V_(A) to the output path P_(H).

Then the addition circuit 24 adds the reference voltage V_(REF) as atolerance for the coincident decision to the signal V_(B) from theoutput path P_(L). The coincidence decision circuit 25 compares thelevel of an addition output signal (V_(B) +V_(REF)) from the additioncircuit 24 with the level of the high level signal V_(A) from the outputpath P_(H), and decides whether the addition signal level is higher thanthe high level signal (V_(B) +V_(REF) >V_(A)) or not. If V_(A) >V_(B)and V_(B) +V_(REF) >V_(B), the coincidence decision circuit 25 decidesthe signal V_(A) is coincident with the signal V_(B). Similarly, ifV_(A) <V_(B) and V_(A) +V_(REF) >V_(B), the coincidence decision circuit25 decides the signal V_(A) is coincident with the signal V_(B).

Therefore, until a time t₀ a decision of the coincidence decisioncircuit 25 is NO (V_(A) is not coincident with V_(B)) because V_(A)>V_(B) and V_(B) +V_(REF) <V_(A), and the coincidence decision circuit25 outputs a low level signal S₁ (L). After the time to the decision isYES (V_(A) is coincident with V_(B)) because V_(A) <V_(B) and V_(A)+V_(REF) >V_(B), and the coincidence decision circuit 25 outputs a highlevel signal S₁ (H).

At the time t₁, the signal V_(B) crosses the signal V_(A), and thesignal S₂ from the level comparator 21 becomes low (V_(A) <V_(B)).Thereby, the path switching circuit 22 connects the low level signalV_(A) to the output path P_(L) and connects the high level signal V_(B)to the output path P_(H) respectively. The addition circuit 24 outputs asignal V_(A) +V_(REF). The coincidence decision circuit 25 compares thesignal V_(A) +V_(REF) with the signal V_(B) and decides whether V_(A)+V_(REF) >V_(B) or not. From the time t₁ to time t₂ the decision is YESbecause V_(B) >V_(A) and V_(A) +V_(REF) >V_(B), and the coincidencedecision circuit 25 outputs a high level signal S₁ (H). After the timet₂ the decision is NO since V_(B) >V_(A) and V_(A) +V_(REF) <V_(B), andthe coincidence decision circuit 25 outputs a low level signal S_(l)(L).

Thus, the coincidence decision circuit 25 decides the signal V_(A) iscoincident with the signal V_(B) during the time from t₀ to t₂. Thebasis of the decision of the coincidence of the two signal levels isthat the signal level from the output path P_(H) is smaller than thesignal level from the addition circuit 26, and the reference voltageV_(REF) provides a tolerance of coincidence. This is generally writtenas follows V(P_(H))>V(P_(L)), and V(P_(L))+V_(REF) >V(P_(H)). It ispossible to arrange the circuit of FIG. 1 by using a general useoperational amplifier and comparator and to provide a small circuit withno adjustment.

FIG. 4 shows a preferred embodiment of a circuit according to thepresent invention. In FIG. 4, the level comparator 21 consists of ananalog comparator using an operational amplifier A₁ and resistors R₁ andR₂, and outputs a high level signal S₂ (H) when an input signal levelV_(A) is higher than an input signal level V_(B) (V_(A) >V_(B)) oroutputs a low level signal S₂ (L) when V_(A) <V_(B). The path switchingcircuit 22 consists of plural analog switches SW₁ -SW₄. When the signalS₂ is high the switches SW₁, SW₃ turn on and the switches SW₂, SW₄ turnoff. In that case (V_(A) >V_(B)), the output path P_(L) is provided withthe low level signal V_(B) and the output path P_(H) is provided withthe high level signal V_(A). Conversely, when the signal S₂ is low(V_(A) <V_(B)), the switches SW₂, SW.sub. 4 turn on and the switchesSW₁, SW₃ turn off, and thereby the output path P_(L) is provided withthe low level signal V_(A) and the output path P_(H) is provided withthe high level signal V_(B). The analog switch consists of a CMOStransistor that is constructed by a parallel combination of a PMOStransistor and an NMOS transistor.

The tolerance generator 23 consists of a voltage divider comprised ofresistors R₃ and R₄ and an operational amplifier A₂ as avoltage-follower circuit. The voltage divider produces the referencevoltage V_(REF) by dividing a power supply voltage V_(a) and theamplifier A₂ outputs the reference voltage V_(REF) only throughimpedance conversion. Similarly, each the operational amplifiers A₃ andA₄ has an arrangement of a voltage-follower circuit with 100%negative-feedback of its output, and outputs the signal V_(A) or V_(B)from output path P_(H) and output path P_(L) respectively. The additioncircuit 24 consists of resistors R₅ -R₈ and an operational amplifier A₅,and adds the reference voltage V_(REF) to the output voltage V_(A) orV_(B) from the output path P_(L).

The coincidence decision circuit 25 consists of an analog comparatorusing resistors R₉, R₁₀ and an operational amplifier A₆. If the outputsignal level from the addition circuit 24 (V_(A), or V_(B) +V_(REF)) ishigher than the output signal level from the output path P_(H) (V_(B) orV_(A)), the coincidence decision circuit 25 outputs a high level signalS₁ (H), or if the output signal level from the addition circuit 24 islower than the output signal level from the output pass P_(H), thecoincidence decision circuit 25 outputs a low level signal S₁ (L).

FIG. 5(A) and FIG. 5(B) are explanatory views that schematically showthe operation of the coincidence decision circuit 25 as described above.FIG. 5(A) shows the case of V_(A) >V_(B), therefore the coincidencedecision circuit 25 outputs a low level signal (L) in a state 1 (V_(B)+V_(REF) <V_(A)) or conversely outputs a high level signal (H) in astate 2 (V_(B) +V_(REF) >V_(A)). FIG. 5(B) shows the case of V_(B)>V_(A), and the coincidence decision circuit 25 outputs the low levelsignal (L) in a state 1 (V_(A) +V_(REF) <V_(B)) and outputs the highlevel signal (H) in a state 2 (V_(A) +V_(REF) >V_(B)).

FIG. 6 shows an example of timing diagrams of output signals in FIG. 4.In a section 1 the time base, V_(A) >V_(B) and the output signal S₂ fromthe level comparator 21 becomes high (H), in response to the signal S₂the path switching circuit 22 connects the input signal V_(A) to theoutput path P_(H) and the input signal V_(B) into the output path P_(L)respectively. The addition circuit 24 adds the signal V_(B) to thesignal V_(REF) and outputs a signal V_(B) +V_(REF). Since V_(B) +V_(REF)<V_(A) in the section 1, the output signal S₁ from the coincidencedecision circuit 25 is low (L), and although V_(A) >V_(B) in section 2,by increasing the signal V_(B) a level of the signal V_(B) +V_(REF)becomes higher than a level of the signal V_(A) (V_(B) +V_(REF) >V_(A))and then the output signal S₁ is high (H). When the signal V_(B) crossesthe signal V_(A) (V_(A) <V_(B)), the level comparator 21 exchanges theconnection from the input signals V_(A), V_(B) to the output pathsP_(L), P_(H), and thereby, the input signal V_(A) is connected to theoutput paths P_(L) and the input signal V_(B) is connected to the outputpaths P_(H). The addition circuit 24 outputs a signal V_(A) +V_(REF).The coincidence decision circuit 25 compares the signal V_(A) +V_(REF)with the signal V_(B). Therefore, the signal V_(A) becomes lower thanthe signal V_(B) in a section 3 (V_(A) <V_(B)), and the output signal S₁remains high (H) (V_(A) +V_(REF) >V_(B)). Then the coincidence decisioncircuit 25 outputs a low level signal (L) in a section 4 because V_(A)<V_(B) and V_(A) +V_(REF) <V_(B).

As described above, the detector according to the present invention isable to vary the decision range of coincidence by adjusting thereference voltage V_(REF) precisely so that it is possible to decide thecoincidence of two input signals V_(A), V_(B) under the condition thatthe input signal V_(A) is nearly equal to the input signal V_(B), byreducing the reference voltage V_(REF). Conversely, it is possible todecide the coincidence of two input signals V_(A), V_(B) under thecondition that the signal V_(A) is quite different from the signal V_(B)by increasing the reference voltage V_(REF). Therefore, an extent ofapproximation for the decision can be set up optionally. To vary thereference voltage V_(REF) a variable resistor may be used instead of theresistor R₃ or R₄. Further, by using an integrated circuit (IC) whichhas four operational amplifiers in a package, the detector can beremarkably reduced in terms of circuit scale to less than theconventional system described above and thereby the circuit in FIG. 4can be constructed using only two small analog ICs.

As described above, the detector according to the present inventionnormally watches for elevation of two signal levels, and by anapproximation of the difference between the two signal levels bycomparison of the signal levels, decides whether one signal level iscoincident with the other signal level when the extent of approximationis within the limit of a predetermined reference voltage. Therefore, thedetector according to the present invention has a distinct advantage ofbeing able to make a decision on coincidence by simple comparison.Further, the detector according to the present invention can be madecheaply by using a general use operational amplifier and a comparator,and the detector can be miniaturized by not adding an adjusting circuit.

I claim:
 1. A method for detecting a coincidence in level of two inputsignals, comprising the steps of;deciding a difference in elevationbetween two input signals, adding a low level signal selected from theinput signals by the decision to a tolerance level signal for decidingone input signal level is coincident with the other input signal level,comparing a result of the addition with a high level signal selectedfrom the input signals by the decision, and deciding one input signallevel is coincident with the other signal level if the level of theresult of addition is higher than the level of the high level signal bythe comparison.
 2. A method for detecting the coincidence of two inputsignals, comprising the steps of;deciding a difference in elevationbetween two input signals, connecting a low level signal selected fromthe input signals to one output path for the low level signal andconnecting a high level signal selected from the input signals toanother output path for the high level signal determined by thedecision, producing a tolerance level for deciding one input signallevel is coincident with the other signal level, adding the low levelsignal from the output path to the tolerance level signal, and comparinga result of the addition with the high level signal from the outputpath, and deciding one input signal level is coincident with the othersignal level if a level of the result of addition is higher than a levelof the high level signal.
 3. An apparatus for detecting the coincidenceof two input signals, comprising;first means for deciding elevationbetween two input signals, second means for connecting a low levelsignal selected from the input signals to one output path for the lowlevel signal and connecting a high level signal selected from the inputsignals to another output path for the high level signal based on adecision output from the first means, third means of producing atolerance level for deciding whether one input signal level iscoincident with another input signal level, fourth means for adding thelow level signal from the output path of the second means to thetolerance level from the third means, and fifth means for comparing theaddition output from the fourth means with the high level signal fromthe output path of the second means, and deciding one input signal levelis coincident with the other input signal level if a level of theaddition output is higher than a level of the high level signal.
 4. Acircuit for detecting the coincidence of two input signals as set forthin claim 3 wherein said first means comprises an analog comparator forcomparing said two input signals to decide the elevation of the twoinput signals.
 5. A circuit for detecting the coincidence of two inputsignals as set forth in claim 3 wherein said second means comprisesanalog switches that connect said low level signal to said output pathfor the low level signal and said high level signal to said output pathfor the high level signal by a control signal corresponding to saiddecision of the elevation of the first means.
 6. A circuit for detectingthe coincidence of two input signals as set forth in claim 3 whereinsaid fourth means comprises an analog addition circuit that adds saidreference voltage from the third means to said low level signal fromsaid output path for the low level signal of the second means, andoutputs an addition output signal.
 7. A circuit for detecting thecoincidence of two input signals as set forth in claim 3 wherein saidfifth means comprises an analog comparator for comparing a level of saidaddition output signal from the fourth means with a level of said lowlevel signal from said output path for the high level signal of thesecond means.
 8. A circuit for detecting the coincidence of two inputsignals as set forth in claim 3 wherein said third means comprises bleedresistors that produce a reference voltage as said tolerance level, andan amplifier for buffering the reference voltage.
 9. A circuit fordetecting the coincidence of two input signals as set forth in claim 8wherein at least one of said bleed resistors consists of a variableresistor for setting said tolerance level optionally.